Description:
ARM Cortex-M3 revision 2.0 running at up to 84 MHz
Memory Protection Unit (MPU)
24-bit SysTick Counter
Thumb®-2 instruction set
Nested Vector Interrupt Controller
2 x 128 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank
32 + 32 Kbytes embedded SRAM with dual banks
16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
Embedded voltage regulator for single-supply operation
POR, BOD and Watchdog for safe reset
Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock
High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default Frequency for fast device startup
Slow Clock Internal RC oscillator as permanent clock for device clock in low power mode
One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Mini Host/Device
Temperature Sensor
15 peripheral DMA (PDC) channels and 6-channel central DMA plus dedicated DMA for High-Speed USB Mini Host/Device and Ethernet MAC
Sleep, Wait and Backup modes, down to 2.5 μA in Backup mode with RTC, RTT, and GPBR
100-lead LQFP – 14 x 14 mm, pitch 0.5 mm
100-ball TFBGA – 9 x 9 mm, pitch 0.8 mm
Industrial (-40° C to +85° C)
USB 2.0 Device/Mini Host: 480 Mbps, 4 Kbyte FIFO, up to 10 bidirectional Endpoints, dedicated DMA
3 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester and LIN support) and one UART
2 TWI (I2C compatible), up to 6 SPIs, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) with up to 2 slots
9-channel 32-bit Timer Counter (TC) for capture, compare and PWM mode, Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
32-bit low-power Real-time Timer (RTT) and low-power Real-time Clock (RTC) with calendar and alarm features
256-bit General Purpose Backup Registers (GPBR)
Ethernet MAC 10/100 (EMAC - RMII) with dedicated DMA
2 CAN Controllers with 8 Mailboxes
True Random Number Generator (TRNG)
63 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination
Six 32-bit Parallel Input/Output Controllers
16-channel 12-bit 1 msps ADC with differential input mode and programmable gain stage
2-channel 12-bit 1 msps DAC
Serial Wire/JTAG Debug Port(SWJ-DP)
Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
IEEE1149.1 JTAG Boundary-scan on all digital pins.
ASF-Atmel software Framework – SAM software development framework
Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
DMA support, Interrupt handlers Driver support
USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
RTOS integration, FreeRTOS is a core component